This is intended to be a collection for custom design rules for KiCAD PCBs that I use more frequently (with KiCAD 7.99). Note that rules further down (within the custom rule definition file) have priority over previous rules and overwrite them.

Clearances

Net class vs. everything

In this example all nets within net class ‚DIO‘ shall maintain 1.5 mm clearance on outer layers and 0.5 mm on inner layers.

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(rule "Clearance: Net class 'DIO' vs. everything (outer layers)"
   (layer outer)
   (constraint clearance (min 1.5mm))
   (condition "A.NetClass == 'DIO' && B.NetClass != 'DIO'"))
(rule "Clearance: Net class 'DIO' vs. everything (inner layers)"
   (layer inner)
   (constraint clearance (min 0.5mm))
   (condition "A.NetClass == 'DIO' && B.NetClass != 'DIO'"))

Pads

(TODO) Stacked unconneced SMD/TH pads

Stakced pads which are unconnected default to different net names therefore generating DRC errors (e.g. ‚unconnected-(U17-Pad40)‘ and ‚unconnected-(U17-Pad40_0)‘).

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(rule "Clearance: Allow shorting of stacked 'no connect' pads"
   (constraint clearance (min -1mm))
   (condition "A.Type == 'Pad' && B.Type == 'Pad' && A.Net != B.Net && A.NetName == 'unconnected-*' && B.NetName == 'unconnected-*'"))

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Vias

Connection width: 0mm for vias of same net

Allow low connection width between very close vias of the same net (usually connected by trace or copper pour anyways).

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(rule "Connection width: 0mm for vias of same net"
   (constraint connection_width (min 0mm))
   (condition "A.Type == 'Via' && B.Type == 'Via' && A.Net == B.Net"))

Annular width: Thermal vias within specific footprint(s)

If thermal vias within pre-defined footprints have a narrower annular ring than the general rule of your current PCB this typically is not a problem for production because they are sourrounded by copper anyways. The following exception must be edited to cover all reference designators required (‚U7‘ and ‚U15‘ in the example).

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(rule "Annular width: Thermal vias within specific footprint(s)"
    (constraint annular_width (min 0.15mm))
    (condition "A.Type == 'Pad' && A.Pad_Type == 'Through-hole'")
    (condition "A.memberOfFootprint('U7') || A.memberOfFootprint('U15')" ))

Net tie/net linker

Net ties remain a pain-in-the-ass in KiCAD as there is no proper checking exceptions within the DRC. Especially, if one builds own compact net ties where the distance of the connecting tracks are low, things become error prone. The following rules deactivates clearance checking for all parts of the net tie footprint (usually pads and a polygons) (e.g. ‚NT1‘ and ‚NT2‘). For very small net ties the nets have to to be specified (2nd rule as an example).

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(rule "Clearance: 0mm for compact net tie components everything"
   (constraint clearance (min 0mm))
   (condition "A.memberOfFootprint('NT1') || A.memberOfFootprint('NT2')"))
(rule "Clearance: 0mm for NT2 nets"
   (constraint clearance (min 0mm))
   (condition "A.NetName == '/Current/I_{Ref}' && B.NetName == '/DAC/CVT_{Ref1718}'"))

Silkscreen

Ignore overlapping silkscreen

(rule "Silkscreen: Ignore overlapping for non-text"
    (constraint silk_clearance (min -1mm))
    (condition "A.Type != 'Text' && B.Type != 'Text'"))
(rule "Silkscreen: Ignore zone overlapping text"
    (constraint silk_clearance (min -1mm))
    (condition "A.Type == 'Zone' && B.Type == 'Text'"))