Date start: 2024-06-20
Date end: 2025-07-24 Operator: FBä

Overview

DUT

No.: 1
BMM version: 0.1.0

Power supply

Switching regulator U3 (MAX17552AUB)

Start-up

Tested between 20V and 60V (still with 2x1mH inductor).

Switching waveforms

Several improvements were made:

• Added snubber to secondary side to dampen resonance and dissipate energy from leakage inductance.
• Chose lower inductance dual inductor (SRF0703-221M) for higher SRF and less leakage inductance.
• Added more primary output capacitance because of the smaller inductor.
• Reduced f_sw for higher efficiency and less effect of leakage inductance on secondary side regulation.
• PFM mode for higher efficiency in majority of situations.

Result:

• Switching frequency as expected (210kHz).
• Switching node waveform is quite clean.

Frequency and mode test

It is “hardest” to supply the isolated switch supply 10Vsw in with low primary output load and in PFM mode. The latter disables negative pri. inductor current for U3 (MAX17552AUB) which also supplies the isolated output. The isolated output must remain well below 20V under all circumstances.

Test configuration:

• Updated parts
  • L3: 2x220µH, C53: 4.4µF (3µF eff.)
  • R_Snub: 1kΩ, C_Snub: 100pF
• Load
  • Primary +10V
    • idle (core: standby (35μA_(typ)), isoSPI: ready (5.1mA_(typ)))
    • idle + 30mA (167Ω/5V)
  • Secondary 10Vsw
    • idle with PG (ca. 1.5mA)
    • idle+8.5mA (using 1.3kΩ/11V)
• f_sw: 210kHz (R191: 200kΩ)
• Modes: Both forced-PWM (safe bet) and PFM

Result: +10V ripple is about 50mVpp at 10mA load on 10Vsw in PWM mode. PFM is especially effective to reduce losses at higher input voltages and light load. As 10Vsw decreases in PFM mode, it might not generate exactly 10V at 10Vsw at high load and (unusally!) low input voltages. Also mind, that 10mA load is more than twice the expected load on 10Vsw. PFM creates about 100mV ripple on +10V when skipping pulses, which is acceptable because of the linear regulator downstream.

Temperature rise

Surprisingly there is greater power loss at a special operating point in PFM than in PWM mode at very low input voltage and maximum load. Increase in temperature is below 20°C (linear post-regulator).

Linear regulator U2 (TPS7A2450DBVR)

Linear regulator puts out stable 5V as expected.

Switch

Power

Start-up

Very similar behaviour from 20..60V supply.

Idle current

This includes one half of the gate date driver U16 (primary side unpowered) and the power good circuitry.

Power-good signal

These levels include various modifications from version 0.1.0 and do not exactly reflect 0.1.2 status.

Measurements at a room temperature of 24..27 °C.

Control

Blocking Sw_En if Oc is low:

Turn-on/turn-off time

Turn-on with 8x IPT012N08N5 assembled, 54V, 100Ω resistive load: ≪5µs for V_GS of >10V

Turn-off with 8x IPT012N08N5 assembled, 54V, 100Ω resistive load: ≪5µs for V_GS of <2V

Isolated gate driver propagation time

Examplary image:

Measurements at a room temperature of 21..22 °C.

AFE

Core states

State “extended balancing” is not used.

isoSPI-port states

V_Ref2Buf

• Output is stable
• Offset to V_Ref2: ≈4µV

Cell balancing

This was tested using fixed 3.7V voltage for all channels, balancing all channels at once, no cooling at all, just laying on the bench at root temperature. Balancing was deactivated in software once a temperature sensor exceeded 80°C.

All channels are visibly active. Note: When all channels are balancing (can’t happen in reality) the hottest spot is the center of the balancing resistors - not the temperature sensors (darker spots above and below).

The balancing current is about 205mA at 3.7V cell voltage. In the follwing pictures only cells 1, 8, 9 and 16 are balanced as they are the most distant from the sensors. It must be verified, hat all all parts’ operating temperatures are within limits if only a few cells (1, 8, 9 and 16) far are actively balancing:

Sensor temperatures were 44.8/45.3°C. There is a substantial temperature gradient which is not. In case more channels are activated, the peak temperature will increase but the temperature difference can be expected to decrease. This way the balancing over-temperature protection using the current sensor positioning is believed to be sufficient.

I2C

800kHZ isoSPI = 400kHz I2C

Auxiliary output

Activating the auxiliary output by bridging J17 works as expected. The level of ManEn drops while the supplying power supply limits the current in these measurements.

On a longer timescale, the firmware activates the aux. output using the logic signal after starting up for three seconds:

The rugged switching FET is not only required for its avalanche behaviour, but gelesenalso to be able to “survive” a slow turn-off of the load. This can happen it ManEn is let go before the AuxEn is activated and the grate voltage slowly drains via R199.

Fan output

This circuitry was already tested on CVTCS-C initial operation.

Start-up with resistive load:

Start-up into high mode with 2.8W fan as load:

Fan shutdown:

This test was conducted still without diodes protecting the IO-expander in case the Bat_-fused is blown. Therefore logic levels are recorded as 5V instead of 4.4V or similar.

Main fuse diagnosis

Diagnosis function works as expected.

Switch voltage measurement diagnosis

Results:

• Works as expected (V_Bat = 51.2V)
  • 500Ω output load: Computed voltage difference is 2.93V
  • Open output: Vsw difference 2.98V
• Increase of 150mV on Vsw input signal during diagnosis.

Pre-charge

EMC

Notes:

• Overshoot ca. 6V (at Vbat of 51.2V) after FET-turn-off
• Snubber on FET/Free wheeling diode possible but not required - only tiny ringing visible.

Function: Low capacitance

Load: 2x GRM32EC72A106KE05 (nom. 20µ/100V, 4.9µV/51.5V) + 1kΩ

Expected ringing after actual pre-charge is resonance of inductor and load capacitance.

Function: High capacitance

Notes:

• Even though the output current is relatively constant vs. output voltage, the (module) I_Bat current measurement only measures the averaged current of the switch. This creates the illusion that the current would rise together with V_Mod, but actually mainly the switch’s duty cycle increases over time.
• A capacity of 25mF with 31mA constant current dummy load is charged within 5s. If the current I_calc is calculated from the change in capacitor voltage (i(t) = C * dV/dt), this actually shows the highest current at the start of the pre-charge process. This is due to the, compared to the situation at the end of the process, steeper rise of current a constant propagation delay of the circuit.

Modification 2: Short Q31-3 to GND (shorts out Q31B)

Removal of M3 ensures better (ensured) start-up behaviour and might delete the source of the double pulses… (?) at the cost of a higher swithcing frequency - especially into short circuits (watch temperature!).